This invention relates to a method for fabricating a semiconductor device in which bipolar, n-MOS, p-MOS transistors are integrated.
In conventional method, the buried layers are formed on the substrate, the single crystalline silicon epitaxial layer of proper thickness is grown on the buried layers, the twin well is formed, and then bipolar, n-MOS, p-MOS, transistors are formed by the conventional method to fabricate these devices in one chip.
But this structure has the disadvantages for high performance and high speed BiCMOS semiconductor IC's. Firstly, it is very difficult to grow the thin epitaxial layer without serious crystal defects and have a sufficiently reproducible epitaxial layer in mass production. Secondly, a thin epitaxial layer is needed for high speed bipolar transistors and a fairly thick epitaxial layer for high performance MOS transistor.